A compact analog active time delay line using SiGe BiCMOS technology

Author

Hamouda, Mahmoud ; Fischer, Georg ; Weigel, Robert ; Ussmueller, T.

Author_Institution

Inst. for Electron. Eng., Univ. of Erlangen-Nuremberg, Erlangen, Germany

fYear

2013

fDate

19-23 May 2013

Firstpage

1055

Lastpage

1058

Abstract

This work discusses the design of a 60ps delay element for UWB analog signals ranging from 0.05 up to 8GHz. The design is implemented using active architecture design which have the advantage of being very compact in area compared to the passive architectures. The proposed architecture is flexible and can be cascaded to have a delay of up to 200ps with a maximum insertion loss of 3dB. The circuit is designed using a low cost 0.25μm 95GHz f_max SiGe-HBT-BiCMOS process technology consuming a power of 121mW. The estimated consumed area of the circuit is 0.49mm².

Keywords

BiCMOS analogue integrated circuits; Ge-Si alloys; delay lines; heterojunction bipolar transistors; semiconductor materials; ultra wideband technology; UWB analog signals; active architecture design; circuit design; compact analog active time delay line; frequency 0.05 GHz to 8 GHz; insertion loss; loss 3 dB; passive architecture; power 121 mW; silicon germanium HBT BiCMOS process technology; size 0.25 mum; time 60 ps; Computer architecture; Delay lines; Delays; Insertion loss; Microprocessors; RLC circuits; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572031

Filename

6572031