DocumentCode
626749
Title
Network partitioning and GA heuristic crossover for NoC application mapping
Author
Yin Zhen Tei ; Marsono, M.N. ; Shaikh-Husin, N. ; Yuan Wen Hau
Author_Institution
Fac. of Electr. Eng., Univ. Teknol. Malaysia, Skudai, Malaysia
fYear
2013
fDate
19-23 May 2013
Firstpage
1228
Lastpage
1231
Abstract
Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic algorithm approach that incorporates network partitioning and heuristic crossover techniques to improve the NoC application mapping. Our experiment on VOPD (video object plane decoder) shows that our proposed method results in only 0.2% to 0.8% communication cost difference compared to global optimal mapping and 6% better communication cost compared to technique using conventional GA.
Keywords
computational complexity; genetic algorithms; logic circuits; microprocessor chips; network-on-chip; GA heuristic crossover; IP cores; NP-hard problem; NoC application mapping; NoC topology; VOPD; genetic algorithm approach; heuristic crossover technique; intellectual property cores; network partitioning; network-on-chip; on-chip communication architecture; optimum core-to-topology mapping; video object plane decoder; Biological cells; Convergence; Genetic algorithms; IP networks; Sociology; Statistics; Topology; Network-on-chip; application mapping; genetic algorithm; network partitioning;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location
Beijing
ISSN
0271-4302
Print_ISBN
978-1-4673-5760-9
Type
conf
DOI
10.1109/ISCAS.2013.6572074
Filename
6572074
Link To Document