Low-energy and low-latency error-correction for phase change memory

Phase change memory (PCM) is a promising candidate for next-generation memory. To lengthen the lifetime of PCM, both transient (soft) and stuck-at (hard) errors need to be corrected. Previous approaches either address only hard errors using error-correcting pointers (ECPs), or employ error-correcting codes capable of correcting six or more errors, which demand high decoding complexity and large storage overhead. Also the verify-after-write needed to generate the ECPs leads to high energy consumption and latency overhead. In this paper, by making use of the property that soft errors are rare and hard errors increase gradually with the number of writes, a novel scheme is proposed to correct both soft and hard errors through integrating 2-error-correcting BCH codes and ECPs. In our design, the ECPs come directly from BCH decoding results. Hence, the energy-consuming verify-after-write and complicated ECP generation process are eliminated. Efficient and low-latency hardware implementations are also developed for BCH en/decoding suitable for PCM applications. Synthesis and power analysis show that the proposed scheme leads to significant overall energy and latency reductions. Moreover, our design can achieve similar or better error protection than prior schemes.