Title :
A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations
Author :
Yikui Jen Dong ; Zhong, Freeman
Author_Institution :
LSI Corp., Milpitas, CA, USA
Abstract :
We investigate the prospect of low-jitter wide frequency range high-speed clocking implementation. A novel architecture features multi-LCVCO with mitigation of dormant VCO leakage current and capacitive modulation is proposed. The new scheme decouples the typical trade-offs between tuning-range, achievable speed and jitter-performances. It enables high frequency low jitter PLL design with sizable tuning range in nowadays highly leaky standard CMOS. A novel self calibration method is presented to seamlessly activate a proper VCO with a proper switched-tuning band to bias the PLL in its optimal operating point. Hence, design requirements for critical circuits including the VCO, the first divide-by-2 and the loop-filter are relaxed. The proposed scheme was implemented and validated in silicon.
Keywords :
CMOS analogue integrated circuits; elemental semiconductors; integrated circuit design; jitter; leakage currents; phase locked loops; silicon; voltage-controlled oscillators; capacitive modulation mitigation; divide-by-2 filter; highly-leaky standard CMOS; leakage current modulation mitigation; loop filter; low-jitter PLL design; low-jitter wide-frequency range high-speed clocking implementation; multiLCVCO; self-calibrating multiVCO PLL scheme; silicon; switched-tuning band; tuning range; Calibration; Jitter; Phase locked loops; Switches; Tuning; Varactors; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572117