DocumentCode :
626794
Title :
SSC tracking analysis and a deeper-SSC estimator
Author :
Yaming Zhang ; Weixin Gai
Author_Institution :
Dept. of Microelectron., Peking Univ., Beijing, China
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
1408
Lastpage :
1411
Abstract :
This paper examines two kinds of bang-bang semidigital dual loop CDR architectures: 2nd-order and 3rd-order. Quantitative analysis is made in detail between the two in the presence of spread spectrum clocking (SSC) which hasn´t been well studied. Moreover, a novel SSC estimator based on 3rd-order architecture is proposed to suppress the frequency-overshoot of conventional 3rd-order CDR happening at the switching points of SSC. The depth of its SSC tracking may be up to 10000ppm at 30 KHz which helps to reduce EMI.
Keywords :
clock and data recovery circuits; electromagnetic interference; interference suppression; phase locked loops; EMI reduction; SSC tracking analysis; analog PLL based clock and data recovery; bang-bang semidigital dual loop CDR architectures; deeper-SSC estimator; spread spectrum clocking; Bandwidth; Clocks; Frequency estimation; Jitter; Steady-state; Switches; Time-frequency analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6572119
Filename :
6572119
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=626794
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