A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Author

Chi-Shin Chang ; Hao-I Yang ; Wei-Nan Liao ; Yi-Wei Lin ; Nan-Chun Lien ; Chien-Hen Chen ; Ching-Te Chuang ; Wei Hwang ; Shyh-Jye Jou ; Ming-Hsien Tu ; Huan-Shun Huang ; Yong-Jyun Hu ; Kan, Paul-Sen ; Cheng-Yo Cheng ; Wei-Chang Wang ; Jian-Hao Wang ; Kuen

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

19-23 May 2013

Firstpage

1468

Lastpage

1471

Abstract

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

Keywords

SRAM chips; UHF integrated circuits; ADAWA scheme; RSNM; adaptive data-aware write-assist scheme; bit rate 1.0 Mbit/s; frequency 800 MHz; low-power CMOS technology; pipeline 6T SRAM; power 23.21 mW; power 6.01 mW; read static noise margin; size 40 nm; temperature 25 degC; variation-tolerant SUWL; variation-tolerant step-up word-line; voltage 1.5 V to 0.7 V; CMOS integrated circuits; Latches; Monte Carlo methods; Pipelines; Random access memory; Semiconductor device measurement; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572134

Filename

6572134