Title :
A FVF based output capacitorless LDO regulator with wide load capacitance range
Author :
Koay, K.C. ; Chong, Sau Siong ; Chan, P.K.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
An output capacitorless low-dropout (LDO) regulator, which applies the proposed Dual Summed Miller Frequency Compensation (DSMFC) on Flipped Voltage Follower (FVF) structure with composite power transistor, is proposed. Validated by UMC 65nm CMOS process, the simulation results have shown that the proposed LDO regulator consumes only 13.2μA at a 1.2V supply, with a dropout voltage of 200mV. At a total of 10pF compensation capacitance, it can support 0-50mA load current for a load capacitance range of 10pF-100nF at typical process and temperature whilst 10pF-10nF at worst condition. The proposed LDO regulator is able to recover in 0.925μs at CL=50pF. The comparison results have shown that the maximum load capacitance is more than two orders of magnitude with respect to those of the FVF LDO counterparts at identical process, supply, quiescent power and compensation capacitance.
Keywords :
CMOS analogue integrated circuits; operational amplifiers; voltage regulators; DSMFC; FVF based output capacitorless LDO regulator; FVF structure; UMC CMOS process; capacitance 10 nF to 100 nF; capacitance 10 pF to 10 nF; composite power transistor; current 0 mA to 50 mA; current 13.2 muA; dual summed miller frequency compensation; flipped voltage follower structure; load capacitance; load capacitance range; load current; output capacitorless low-dropout regulator; size 65 nm; voltage 1.2 V; voltage 200 mV; Capacitance; Gain; Poles and zeros; Power transistors; Regulators; System-on-chip; Time-frequency analysis;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572139
