Title :
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL
Author :
Urano, Yuta ; Won-Joo Yun ; Kuroda, Tadahiro ; Ishikuro, Hiroki
Author_Institution :
Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
Abstract :
This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.
Keywords :
clock and data recovery circuits; delay lines; delay lock loops; edge detection; jitter; time-digital conversion; NRZ signaling; TDC combined DLL; all-digital CDR; bit rate 1 Gbit/s; bit rate 2.3 Gbit/s; clock and data recovery circuit; delay line; delay-locked-loop; edge detection; pulse-based signal communication; time 5.44 ps; time-to-digital converter; voltage 0.7 V; voltage 1 V; waveform evaluation; Clocks; Delay lines; Delays; Image edge detection; Jitter; Optical signal processing; Power demand;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572161
