Title :
Analog implementation of encoded neural networks
Author :
Larras, Benoit ; Lahuec, Cyril ; Arzel, Matthieu ; Seguin, Fabrice
Author_Institution :
Technopole Brest Iroise, Electron. Dept., Telecom Bretagne, Brest, France
Abstract :
Encoded neural networks mix the principles of associative memories and error-correcting decoders. Their storage capacity has been shown to be much larger than Hopfield Neural Networks´. This paper introduces an analog implementation of this new type of network. The proposed circuit has been designed for the 1V supply ST CMOS 65nm process. It consumes 1165 times less energy than a digital equivalent circuit while being 2.7 times more efficient in terms of combined speed and surface.
Keywords :
CMOS analogue integrated circuits; content-addressable storage; decoding; error correction codes; neural nets; Hopfield neural networks; ST CMOS process; analog implementation; associative memories; encoded neural networks; error-correcting decoders; size 65 nm; storage capacity; voltage 1 V; Analog circuits; Associative memory; Biological neural networks; CMOS integrated circuits; Digital circuits; Power demand;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572170
