High-performance multiplierless transform architecture for HEVC

In this paper, a high-performance multiplierless VLSI architecture for the transform applied in the emerging video coding standard-High Efficiency Video Coding (HEVC) is presented. The proposed architecture can support a variety of transform sizes from 4×4 to 32×32, and some simplification strategies are adopted during the implementation, such as reusing part of a larger sized transform structure reused by smaller ones, and turning multiplications by constant into shift and sum operations. Synthesis results on the FPGA platform indicate that the proposed design can double the throughput compared with previous work, with almost the same hardware cost. Moreover, synthesis results under 45nm technology show that it can support real-time processing of 4Kx2K (4096×2048, 30fps) video sequences. When a comparison index called “data throughput per unit area” is adopted, the proposed architecture is almost five times more efficient than is the previous design.