• DocumentCode
    626862
  • Title

    Muller C-element based Decoder (MCD): A decoder against transient faults

  • Author

    Yangyang Tang ; Boutillon, E. ; Winstead, Chris ; Jego, Christophe ; Jezequel, Michel

  • Author_Institution
    Lab.-STICC, Univ. de Bretagne Sud, Lorient, France
  • fYear
    2013
  • fDate
    19-23 May 2013
  • Firstpage
    1680
  • Lastpage
    1683
  • Abstract
    This work extends the analysis and application of a digital error correction method called Muller C-element Decoding (MCD), which has been proposed for fault masking in logic circuits comprised of unreliable elements. The proposed technique employs cascaded Muller C-elements and XOR gates to achieve efficient error-correction in the presence of internal upsets. The error-correction analysis of MCD architecture and the investigation of C-element´s robustness are first introduced. We demonstrate that the MCD is able to produce error-correction benefit in a high error-rate of internal faults. Significantly, for a (3,6) short-length Low Density Parity Check (LDPC) code, when the decoding process is internally error-free the MCD achieves also a gain in terms of decoding performance by comparison to the well-known Gallager Bit-Flipping method. We further consider application of MCD to a general-purpose fault-tolerant model, coded Dual Modular Redundancy (cDMR), which offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures.
  • Keywords
    decoding; fault tolerance; logic circuits; logic gates; parity check codes; Gallager bit-flipping method; MCD architecture; Muller C-element decoding; Muller C-element-based decoder; XOR gates; cDMR; coded dual modular redundancy; contemporary logic systems; decoding process; digital error correction method; fault masking; fault-tolerant model; internal upsets; logic circuits; low-redundancy error-resilience; nanoeletronic architectures; short-length LDPC code; short-length low density parity check code; transient faults; Circuit faults; Computer architecture; Decoding; Iterative decoding; Logic gates; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
  • Conference_Location
    Beijing
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4673-5760-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2013.6572187
  • Filename
    6572187