Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis

As technology scaling, three-dimensional integrated circuits (3D-ICs) are emerging as a promising solution to address the challenges in system on chips (SoCs). Moreover, it´s a necessity to design an efficient Network-on-Chip (NoC) topology for the interconnection issues of 3D SoCs. In this paper, we propose a topology-aware floorplanning method to determine the power-performance efficient 3D NoC topology. Unlike the previous works which explore the path allocation of the NoC components and Through-Silicon Vias (TSVs) assignment after the floorplan of cores is fixed, we integrate these steps (the clustering of cores + the placement of cores and switches + the path allocation + the TSV-aware topology evaluation) within the 3D floorplanning procedure. Experimental results show the effectiveness of our method.