Title :
A 0.3mm2 10-b 100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS
Author :
Nicholson, Andrew ; Jenkins, J. ; Irfansyah, Astria Nur ; Politi, Nonie ; van Schaik, Andre ; Hamilton, Tara J. ; Lehmann, T.
Author_Institution :
Sch. of Electr. Eng. & Telecommun., Univ. of New South Wales, Sydney, NSW, Australia
Abstract :
We present a standard pipelined ADC design using Nauta structure differential op-amps as an alternative to traditional analog op-amps. The six stage pipelined ADC is capable of running at 100MS/s and achieves 8 bit resolution under simulations. The research is focused on the path to scaling to deep sub-micron CMOS and finding alternatives to the reduced gain and low output voltage swing of traditional analog op-amp designs. The Nauta structure op-amp allows us to produce one of the smallest reported areas for a 180nm pipelined ADC occupying only 0.3mm2 for a 10 bit 100MS/s pipelined ADC.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; operational amplifiers; Nauta structure differential op-amps; deep sub-micron CMOS; six-stage pipelined ADC; standard pipelined ADC design; traditional analog op-amp design; Ash; CMOS integrated circuits; Clocks; Gain; Inverters; Layout; Pipelines; 180nm CMOS; Analog to Digital Conversion; Nauta structure; Pipelined ADC;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572222
