A 100Gb/s quad-rate transformer-coupled injection-locking CDR circuit in 65nm CMOS

This paper presents an injection-locking clock and data recovery circuit (CDR) for serial link receivers. A transformer-coupled injection-locking scheme with all passive components is proposed to lock the quadrature voltage controlled oscillator (QVCO) to align the received data. The quad-rate CDR successfully regenerates the serial 100 Gb/s PRBS 2³¹-1 data into 4 parallel data streams at 25 Gb/s. The fabricated chip occupies 1.92 mm² in 65 nm standard CMOS process with recovered data peak-to-peak jitter of 0.84ps and consumes 130 mW power with 1.0-V supply.