An improved push-pull driver using 0.13μm CMOS

High speed, large voltage swing, low power and robust driver circuit is required for the recent silicon photonics based optical link. Unlike the popular CML approach; this work applies the replica biasing function to cascoded push pull driver. We demonstrate that the proposed approach significantly increases the speed of driver, moderately decreases the power consumption, and strengthen the robustness of driver. Two different design examples are fabricated using IBM-8RF 1P8M 0.13μm CMOS process. At typical process corner, post layout simulation results show that when driving 50 Ohm load at the speed of 10 GB/s, the proposed driver can provide 16dB gain with its output voltage swing at 4.0 Vpp (differential) and the power consumption less than 262mW.