DocumentCode
626928
Title
Low complexity LFSR based bit-serial montgomery multiplier in GF(2m)
Author
Huapeng Wu
Author_Institution
Dept. of ECE, Univ. of Windsor, Windsor, ON, Canada
fYear
2013
fDate
19-23 May 2013
Firstpage
1962
Lastpage
1965
Abstract
Montgomery multiplication in GF(2m) is defined as ABr-1 mod f(α), where f(x) is the irreducible polynomial defining the field and r is a fixed field element. In this paper, a low complexity Montgomery multiplier in GF(2m) is proposed with r=αm-1 or αm. Linear feedback shift register (LFSR) is adopted as the main module for the presented architecture. It is shown that the proposed multiplier has lower space complexity than any of the existing similar works we found in the literature. The time complexity of the proposed multiplier is slightly higher than the best result among the existing works.
Keywords
shift registers; GF(2m); LFSR; fixed field element; linear feedback shift register; low-complexity LFSR-based bit-serial Montgomery multiplier; space complexity; time complexity; Complexity theory; Computer architecture; Delays; Finite element analysis; Logic gates; Polynomials; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location
Beijing
ISSN
0271-4302
Print_ISBN
978-1-4673-5760-9
Type
conf
DOI
10.1109/ISCAS.2013.6572253
Filename
6572253
Link To Document