A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator

Author

Kumar, Y.B.N. ; Caracciolo, H. ; Bonizzoni, Edoardo ; Parra, A. ; Maloberti, Franco

Author_Institution

Dept. of Electr. Eng., UT Kharagpur, Kharagpur, India

fYear

2013

fDate

19-23 May 2013

Firstpage

1998

Lastpage

2001

Abstract

This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.

Keywords

CMOS integrated circuits; body area networks; sigma-delta modulation; CMOS prototype; IF; bandwidth 100 kHz; bandwidth 2.6 MHz; discrete time quadrature band-pass ΣΔ modulator; frequency 20 MHz; intermediate frequency; power 1.96 mW; sampling frequency; size 0.18 mum; wireless body area networks; Band-pass filters; Bandwidth; Frequency modulation; Gain; Signal to noise ratio; Wireless sensor networks; Analog-to-Digital conversion; band-pass ΣΔ modulation; complex filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572262

Filename

6572262