DocumentCode :
626947
Title :
A 15-bit two-step sigma-delta ADC with embedded compression for image sensor array
Author :
Mengyun Yue ; Dong Wu ; Zheyao Wang
Author_Institution :
Inst. of Micro-Electron., Tsinghua Univ., Beijing, China
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
2038
Lastpage :
2041
Abstract :
This paper presents a novel incremental Σ-Δ ADC using two-step conversion and the fully-floating double-sampling integrator to greatly reduce the converting time. With a special procedure to solve the accuracy loss problem, the resolution of ADC is improved by one bit at the same time. What´s more, another comparison is added during the conversion to detect redundant pixels in the image so that data compression is achieved in a simple way.
Keywords :
data compression; image sensors; sampling methods; sigma-delta modulation; accuracy loss problem; data compression; embedded compression; fully-floating double-sampling integrator; image sensor array; incremental Σ-Δ analogue-digital conversion; redundant pixels; two-step sigma-delta ADC; word length 15 bit; Accuracy; Capacitors; Clocks; Image coding; Image resolution; Image sensors; Noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6572272
Filename :
6572272
Link To Document :
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