Title :
3.5-D integration: A case study
Author :
Bobba, Shashikanth ; Gaillardon, Pierre-Emmanuel ; Seiculescu, Ciprian ; Pavlidis, Vasilis F. ; De Micheli, G.
Author_Institution :
Integrated Syst. Lab., EPFL, Lausanne, Switzerland
Abstract :
Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred as 3-D TSV integration, and 3D monolithic integration. In this paper, we present a hybrid integration scheme that combines these two approaches, taking into account their existing technology limits, into a disruptive paradigm called 3.5-D integration. Our novel integration supports circuit-partitioning both at the gate and block level with unprecedented benefits in cost. To demonstrate the effectiveness of 3.5-D integration, we chose as case study a 288-core MPSoC and we made hypothesis on the manufacturing and test cost. We argue a potential 20% decrease in the manufacturing cost and 30% decrease in the test cost when compared to 3-D TSV integration. In order to study the performance improvement of the MPSoC, we benchmarked various blocks of the core and the on-chip interconnection network, connecting all the cores. Our study shows large improvement in performance of the core (average of 11.5%) and latency (average of 24%) of the Network-on-Chip (NoC) for the 3.5-D integration when compared to the corresponding 3-D TSV implementation.
Keywords :
costing; integrated circuit interconnections; integrated circuit manufacture; integrated circuit testing; monolithic integrated circuits; multiprocessing systems; multiprocessor interconnection networks; network-on-chip; three-dimensional integrated circuits; 288-core MPSoC; 3.5D integration; 3D integrated system; 3D monolithic integration; NoC; TSV; circuit-partitioning; cost testing; diverse manufacturing cost technique; multiprocessors system-on-chip; network-on-chip; on-chip interconnection network; through-silicon-vias; Delays; Libraries; Manufacturing; Stacking; Standards; System-on-chip; Through-silicon vias;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572285