A SAR ADC with energy-efficient DAC and tri-level switching scheme

Author

Kuan-Ting Lin ; Kea-Tiong Tang

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2013

fDate

19-23 May 2013

Firstpage

2243

Lastpage

2246

Abstract

This paper presents a 10-bit successive approximation register (SAR) ADC with an energy-efficient switching approach of capacitive DAC. The proposed switching method lessens the dynamic offset effect coming from the asymmetric capacitive switching. A tri-level algorithm is applied additionally to make the ADC more power-efficient and is implemented with switching-capacitive voltage generator without consuming static power. It consumes 3.87μW at 0.5V supply and 1.28MS/s sampling rate, and achieves ENOB of 9.69-bit and FOM of 3.66 fJ/conversion-step. This SAR ADC has been fabricated by TSMC 90nm CMOS process technology.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; digital-analogue conversion; SAR ADC; TSMC CMOS process technology; asymmetric capacitive switching; capacitive DAC; dynamic offset effect; energy-efficient DAC; energy-efficient switching approach; power 3.87 muW; size 90 nm; successive approximation register; switching-capacitive voltage generator; tri-level switching scheme; voltage 0.5 V; Capacitors; Energy efficiency; Generators; Logic gates; Solid state circuits; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572323

Filename

6572323