Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory

Author

Mu-Shih Yeh ; Yung-Chun Wu ; Kuan-Cheng Liu ; Min-Feng Hung ; Yi-Ruei Jhan ; Nan-Heng Lu ; Ming-Hsien Chung ; Min-Hsin Wu

Author_Institution

Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

13

Issue

4

fYear

2014

fDate

Jul-14

Firstpage

814

Lastpage

819

Abstract

This paper develops the n-channel and p-channel twin poly-Si fin field-effect transistor nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results demonstrate that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.6 V after 10⁴ program and erase cycles, and after 10 years, the charge is 53.4% of its initial value. In the future, it can be applied in multilayer Si ICs in fully functional system-on-panel, active-matrix liquid-crystal display and 3-D stacked flash memory.

Keywords

MOSFET; nanowires; random-access storage; silicon; 3D stacked flash memory; N-channel nonvolatile memory; P-channel nonvolatile memory; Si; active matrix liquid crystal display; field effect transistor; memory window; nanowires; program-erase efficiency; twin poly-Si FinFET; Educational institutions; FinFETs; Flash memories; Logic gates; Nonvolatile memory; Thin film transistors; 3-D; ??-gate; Fin field-effect transistor (FinFET); flash memory; nanowires (NWs); nonvolatile memory (NVM); twin poly-Si;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2014.2323983

Filename

6815775