Title :
A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS
Author :
Yousry, Ramy ; Park, Heejung ; E-Hung Chen ; Yang, Chih-Kong Ken
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
The design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS is described. Accuracy requirements are met without compromising the high-speed performance by using trimming-based offset cancellation. The ADC can be configured to work as a 3-bit, a 4-bit, or a 5-bit ADC with maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.48LSB and 0.35LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv-step and the active area is 0.13 mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS; DNL; INL; differential nonlinearity; digitally-calibrated reconfigurable flash ADC; high-speed reconfigurable analog-to-digital converter; maximum integral nonlinearity; size 65 nm; trimming-based offset cancellation; word length 3 bit; word length 4 bit; Accuracy; CMOS integrated circuits; Calibration; Clocks; Receivers; Resistors; Tuning;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572373
