A self-calibrated 10-bit 1 MSps SAR ADC with reduced-voltage charge-sharing DAC

A wide range of applications, including wireless sensor networks (WSN) and biomedical, motivate the design of energy-efficient analog-to-digital converters (ADCs). We propose and discuss the design of an ultra-low power charge-sharing successive approximation ADC. The proposed ADC employs an internal step-down voltage regulator to reduce the energy spent on the digital-to-analog converter (DAC), and we demonstrate that this approach leads to a 5× reduction in the DAC power consumption. Moreover, a self-calibration technique is implemented in order to mitigate the impact of process variations on the ADC linearity. Simulation results show that the proposed 10-bit ADC, designed in a 90 nm technology, consumes 1.79 μW from a 1V supply, while sampling at 1 MSps and providing 9.34 effective bits (mean values based on Monte-Carlo simulation). The achieved figure-of-merit (FOM) of 2.87 fJ/conversion step (mean value) places this ADC among the state-of-the-art designs in low-speed moderate-resolution ADCs.