A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL

Author

Bohan Wu ; Weixin Gai ; Te Han

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2013

fDate

19-23 May 2013

Firstpage

2464

Lastpage

2467

Abstract

A novel frequency search algorithm is proposed in this paper to achieve fast locking in all digital PLL (ADPLL) with no phase tracking being required. According to phase and frequency error, the normalized tuning word (NTW) is calculated so that the output frequency reaches the desired frequency immediately. As the non-idealities, such as DCO gain estimation error and TDC finite resolution, greatly affect the accuracy of the calculation, the output frequency is continuously measured and frequency error is averaged to minimize those impacts. With 0.13um CMOS process, the proposed ADPLL operates at 2.7 GHz and achieves 0.35 us locking time while consuming 7.47mW.

Keywords

CMOS digital integrated circuits; digital phase locked loops; search problems; ADPLL; CMOS process; DCO gain estimation error; NTW; TDC finite resolution; digital PLL; fast locking; frequency 2.7 GHz; frequency error; frequency search algorithm; normalized tuning word; phase error; phase tracking; power 7.47 mW; size 0.13 mum; time 0.35 mus; Bandwidth; Estimation error; Frequency estimation; Measurement uncertainty; Phase frequency detector; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572378

Filename

6572378