Clock and data recovery module in 90nm for 10Gbps serial link with −18dB channel attenuation

A clock and data recovery (CDR) module in 90nm CMOS, for a 10Gbps serial link, integrated with a -18dB attenuation channel, is presented. A novel dual-loop CDR with separate charge pumps for high-gain frequency acquisition, and low-gain phase tracking has been introduced. The CDR utilizes a full rate architecture with a single VCO along with a selection logic for switching to the desired charge pump, resulting in a 4.2mW power consumption from the VCO. A current-steering charge pump with DCVSL inputs reduced the glitches in the up and down currents thereby reducing the ripples on the control voltage to 1mV in the locked condition. An rms and peak periodic jitter of 0.382ps and 0.759ps respectively were achieved with a PRBS sequence of 2⁷ bits, resulting in a design compliant with SONET OC-192 specifications.