Overclocking datapath for latency-error tradeoff

Relaxing constraints of 100% accuracy in datapath can provide the freedom to create designs with better performance or energy efficiency. This paper develops probabilistic models, which enable us to explore these trade-offs for key arithmetic primitives. We show that because specific input patterns are required to cause timing violations and that these patterns arise rarely, a lower expected error can be attained by allowing some timing variations to occur, instead of reducing the precision of a circuit to meet a target latency. Experiments show that a mean reduction of 5.6× ~ 36.7× in error expectation and an improvement of 7.2dB ~ 19.7dB in signal-to-noise ratio can be obtained for practical applications.