Effects of numerical noise floor on the accuracy of time domain noise analysis in circuit simulators

This paper is concerned with the time-domain simulation of circuits including noise sources. In general, when a circuit admits a steady-state solution, small signal analyses are used to determine noise effects. There is a class of circuits (e.g., fractional PLLs based on ΔΣ modulators and forced oscillators) not admitting a steady-state solution with a period reasonable low multiple of the characteristic time scales of the circuit. In commercial analog simulators, time domain noise analyses have been implemented by “extending” linear multi-step integration methods or by introducing sampled versions of noise generators. Through a set of basic benchmark circuits, we show that these extensions are often affected by a relevant numerical noise floor hiding the effects of noise sources and drastically limiting the applicability of time domain noise analysis.