A comparative overview of high power handling CMOS switches and their recent applications in RF front ends

In this publication, techniques for high power handling capability of RF switches in bulk CMOS are investigated and compared. These allow reconfigurable power amplifiers (PAs) or radio front ends for Watt level communication standards if combined with approaches for high isolation. Special care is taken to assess the applicability of the solutions for monolithic integration in scaled CMOS processes. Results are shown with power handling capability as high as 34dBm in a 32nm CMOS process. Recent applications for RF switches in front ends or reconfigurable PAs are analyzed. They enable large DC current reduction in back-off with stage bypassing and load adaptation concepts. Up to 50% DC current reduction for low output power is reported. This greatly improves the average PA efficiency for varying envelope signals without the efforts of more sophisticated solutions like envelope tracking.