Partial controller retiming in high-level synthesis

Various optimization techniques of high-level synthesis (HLS) have been studied for improving clock frequency. However, they focus only on the datapath and cannot handle the controller delay even though most critical paths lie across the controller and datapath (i.e., from state registers in the controller to storage units in the datapath) and the controller delay occupies the non-negligible portion of the paths. This paper proposes a novel HLS technique to remove such controller delays. Our method, “Register-Transfer (RT) level register retiming”, is applied to only parts of the control logic, which generate control signals of multiplexers (MUXs) on critical paths, in such a way that generates and stores the signals into registers in the previous cycle. It then lets the MUXs obtain their control signals directly from the registers, leading to reduction in critical path delay. Experiments on several benchmark programs demonstrate that our RT-level retiming can achieve comparable clock improvement while mitigating area overhead, compared with conventional gatelevel retiming.