Title :
From multicore simulation to hardware synthesis using transactions
Author :
Anane, A. ; Aboulhamid, El Mostapha
Author_Institution :
Univ. de Montreal, Montréal, QC, Canada
fDate :
May 31 2013-June 1 2013
Abstract :
With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become necessary. This paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, we were able to achieve an automatic high-level synthesis flow. Indeed, we kept the same object oriented programming concepts to describe the architecture of high-level models, such as encapsulation and interfacing. However, unlike SystemC, the behaviour is no longer described as processes and events but as transactions. Transactions can be seen as atomic actions interacting through shared variables. Then, we transform such high level translational model to a SystemC behavioral model ready to be synthesized by a behavioral synthesizer.
Keywords :
integrated circuit modelling; microprocessor chips; multiprocessing systems; network synthesis; .NET introspection; SystemC behavioral model; automatic high level synthesis flow; behavioral synthesizer; concurrency model; digital systems; hardware synthesis; high level translational model; multicore simulation; object oriented programming; Adaptation models; Hardware; Object oriented modeling; Protocols; Registers; Schedules; Semantics; Design methodology; Emulation; High level synthesis; Transactions;
Conference_Titel :
Electronic System Level Synthesis Conference (ESLsyn), 2013
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-6414-0