• DocumentCode
    627634
  • Title

    Pre- and post-scheduling memory allocation strategies on MPSoCs

  • Author

    Desnos, Karol ; Pelcat, Maxime ; Nezan, Jean-Francois ; Aridhi, Slaheddine

  • Author_Institution
    IETR, INSA Rennes, Rennes, France
  • fYear
    2013
  • fDate
    May 31 2013-June 1 2013
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper introduces and assesses a new method to allocate memory for applications implemented on a shared memory Multiprocessor System-on-Chip (MPSoC). This method first consists of deriving, from a Synchronous Dataflow (SDF) algorithm description, a Memory Exclusion Graph (MEG) that models all the memory objects of the application and their allocation constraints. Based on the MEG, memory allocation can be performed at three different stages of the implementation process: prior to the scheduling process, after an untimed multicore schedule is decided, or after a timed multicore schedule is decided. Each of these three alternatives offers a distinct trade-off between the amount of allocated memory and the flexibility of the application multicore execution. Tested use cases are based on descriptions of real applications and a set of random SDF graphs generated with the SDF For Free (SDF3) tool. Experimental results compare several allocation heuristics at the three implementation stages. They show that allocating memory after an untimed schedule of the application has been decided offers a reduced memory footprint as well as a flexible multicore execution.
  • Keywords
    data flow graphs; multiprocessing systems; scheduling; storage allocation; system-on-chip; MEG; SDF For Free; SDF algorithm description; SDF3 tool; allocation heuristics; application multicore execution; memory allocation; memory exclusion graph; memory objects; multiprocessor system-on-chip; random SDF graphs; reduced memory footprint; shared memory MPSoC; synchronous dataflow; Memory management; Multicore processing; Parallel processing; Resource management; Runtime; Schedules; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic System Level Synthesis Conference (ESLsyn), 2013
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4673-6414-0
  • Type

    conf

  • Filename
    6573219