Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis

The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due to the programmable interconnect overhead. Three-Dimensional (3D) integration is a promising technology to reduce wire lengths. We present a 3D design optimization methodology leveraged on Through Silicon Via (TSVs) to re-distribute the Tree interconnects into multiple stacked active layers using a tree-level horizontal break-point based on interconnect delay and to optimize the inter-layer heat dissipation. Nonetheless TSVs require a significant silicon area compared to planar interconnects and also bring critical challenges to the design of 3D ICs. In this paper we propose an architectural level interconnect and area optimization solution to minimize TSV count and programmable interconnects without compromising the FPGA performance. TSVs are also used very effectively to control the increase in inter-layer temperature of 3D ICs. We propose a TSV based 3D thermal optimization model for Tree-based FPGA. The experimental results from 3D Tree-based FPGA shows a 40% reduction of TSV count, 37% reduction in interconnect area and 28% reduction in power consumption.