Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters

Author

Mroszczyk, Przemyslaw ; Dudek, Piotr

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. of Manchester, Manchester, UK

fYear

2013

fDate

16-19 June 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents the analysis and design of a simple one-stage tunable delay gate with improved matching properties as compared with the commonly used “current starved inverter”. The operation of two delay lines employing these structures in a standard 90 nm CMOS technology was verified based on the post layout mismatch Monte Carlo simulations. Accounting for the fabrication mismatch, the delay generated by the proposed “output-split inverter” (OSI) circuit is about 10-30% more accurate as compared to the conventional current starved inverter occupying the same chip area.

Keywords

CMOS logic circuits; Monte Carlo methods; delay lines; integrated circuit layout; logic design; logic gates; CMOS technology; OSI circuit; current starved inverter; delay lines; fabrication mismatch; improved matching properties; one-stage tunable delay gate; output-split inverter circuit; post layout mismatch Monte Carlo simulations; size 90 nm; timing parameter; tunable CMOS delay gate; Delay lines; Delays; Discharges (electric); Inverters; Logic gates; Open systems; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International

Conference_Location

Paris

Print_ISBN

978-1-4799-0618-5

Type

conf

DOI

10.1109/NEWCAS.2013.6573595

Filename

6573595