DocumentCode :
62777
Title :
A 16 nm 128 Mb SRAM in High- 
Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications
Author :
Yen-Huei Chen ; Wei-Min Chan ; Wei-Cheng Wu ; Hung-Jen Liao ; Kuo-Hua Pan ; Jhon-Jhy Liaw ; Tang-Hsuan Chung ; Quincy Li ; Chih-Yung Lin ; Mu-Chi Chiang ; Shien-Yang Wu ; Chang, Joana
Author_Institution :
Div. of Memory Design Solution, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
Volume :
50
Issue :
1
fYear :
2015
fDate :
Jan. 2015
Firstpage :
170
Lastpage :
177
Abstract :
A 128 Mb 0.07 μm2 6T high-density SRAM bitcell with write-assist circuitry has been successfully implemented using 16 nm high-k metal gate FinFET technology. This study proposes two write-assist techniques: 1) suppressed coupling signal negative bit-line (SCS-NBL) technique and 2) write recovery enhanced lower cell-VDD (WRE-LCV) technique to reduce the SRAM minimal supply voltage. The area overheads of these two techniques are 2% and 3%, respectively. The silicon data show that both of these techniques can improve overall SRAM VMIN performance by more than 300 mV at the 95th percentile.
Keywords :
MOSFET; SRAM chips; high-k dielectric thin films; SCS-NBL technique; SRAM minimal supply voltage; WRE-LCV technique; high-density SRAM bitcell; high-k metal gate FinFET technology; silicon data; size 16 nm; storage capacity 128 Mbit; suppressed coupling signal negative bit-line technique; write recovery enhanced lower cell-VDD technique; write-assist circuitry; write-assist techniques; Couplings; FinFETs; Logic gates; Metals; Random access memory; Timing; Bitcell; FinFET; SRAM; high-k metal gate; write-assist technique;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2014.2349977
Filename :
6894644
Link To Document :
