Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits

Recent studies have shown that transistor variability and ageing phenomena are responsible for variation of transconductance (g_m) and drain current (I_D) in MOSFETs. It is therefore important to perform sensitivity analysis at the earliest design stage in order to minimize effects of ageing. It is however not trivial to perform sensitivity analysis analytically because the 1-V characteristics of modern transistors can not modeled without using complicated expressions. In this paper, We propose a technique that utilizes the transconductance-to-drain current ratio (g_m/I_D) of a transistor to captures the sensitivity of a circuit. This technique is applicable to transistors biased in all regions of operations. To explore the effectiveness of the proposed technique in practical circuit design, the sensitivity of a common source amplifier is analyzed. The proposed technique has an accuracy of ± 15 % between 4 <; g_m/I_D<; 28.