A DAC mismatch calibration technique for multibit ΣΔ modulators

A technique for the calibration of DAC (digital to analog converter) mismatch errors in multibit ΣΔ modulators (SDM) is presented. It consists of two parts: the first is a measurement technique to obtain the relative mismatch of each feedback DAC element. The second is a correction method applied to the modulator output to correct for the effect of DAC non linearity. The proposed technique works completely in the background. The paper presents a detailed analysis of the possible error sources affecting the accuracy of the calibration, as well as a comparison with other state of the art techniques. The technique is applied to a 3rd order SDM showing almost ideal characteristics after calibration.