Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults

With the shrinking of dimensions, not only the attacks but also transient faults became important concerns of cryptographic processors based on deep submicron technologies. Fault tolerance is achieved by adding redundancy (area, time and information). Motivated by the need of effective designs, we propose a method to characterize the efficiency of fault-tolerant techniques considering both the fault tolerance and the cost penalty. It allows to select the effective technique according to gate reliability. In this paper, we analyze two typical fault-tolerant AES S-Boxes. The results show that parity checking is a good solution for the gate reliability q <; 0.9987, while the Triple Modular Redundancy (TMR) is more suitable for the case of high gate reliability.