Design methodology of an ASIC TRNG based on an open-loop delay chain

Many applications require unpredictable randomly generated numbers. This paper presents a lightweight architecture of a high speed true random number generator (TRNG) and its ASIC implementation. The proposed TRNG randomness is extracted from the observation of the final state of a chain of bistable elements after putting them in a metastable state. The ASIC design methodology targets the CMOS 65 nm technology from STMicroelectronics (STM). It allows to validate the TRNG behavior and evaluate the randomness in different working conditions. Results of standard statistical tests are also presented to validate the TRNG ASIC structure.