DocumentCode :
628359
Title :
Electrical investigation and reliability of 3D integration platform using Cu TSVs and micro-bumps with Cu/Sn-BCB hybrid bonding
Author :
Yao-Jen Chang ; Cheng-Ta Ko ; Zhi-Cheng Hsiao ; Cheng-Hao Chiang ; Huan-Chun Fu ; Tsung-Han Yu ; Cheng-Han Fan ; Wei-Chung Lo ; Kuan-Neng Chen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
64
Lastpage :
70
Abstract :
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250°C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Keywords :
copper alloys; integrated circuit bonding; integrated circuit reliability; leakage currents; three-dimensional integrated circuits; tin alloys; 3D integration platform; 3D integration scheme; Cu-Sn; backside RDL formation; backside process; copper TSV; corrosion; daisy chain feature; electrical characteristics; electrical investigation; electrical properties; electrical reliability; fine-pitch hybrid bonding; humidity test; leakage current improvement; leakage current structures; low temperature hybrid bonding; microbumps; multiple AC current stressing; oxidation; reliability tests; sealing ability; temperature 250 C; thermal cycling test; wafer thinning; wafer-level three-dimensional integration scheme; Bonding; Kelvin; Leakage currents; Reliability; Resistance; Through-silicon vias; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575551
Filename :
6575551
Link To Document :
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