DocumentCode :
628360
Title :
Assembly of 3D chip stack with 30μm-pitch micro interconnects using novel arrayed-particles anisotropic conductive film
Author :
Yu-Wei Huang ; Yu-Min Lin ; Chau-Jie Zhan ; Su-Tsai Lu ; Shin-Yi Huang ; Jing-Ye Juang ; Chia-Wen Fan ; Su-Ching Chung ; Jon-Shiou Peng ; Su-Mei Chen ; Yu-lan Lu ; Pai-Cheng Chang ; Lau, John H.
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
71
Lastpage :
76
Abstract :
As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtai- ed by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.
Keywords :
acoustic tomography; delamination; fine-pitch technology; gold alloys; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; nickel alloys; scanning electron microscopy; silicon; thermal expansion; thermal stresses; three-dimensional integrated circuits; 3D chip stacking assembly; ACF delamination; C2C module; CTE; Ni-Au; TCT; THST; adhesion strength; adhesion test; adhesive flow phenomenon; adhesive matrix; anisotropic conductive film; chip stack reliability; chip warpage; chip-to-chip stack module; coefficient of thermal expansion; daisy-chain resistance variation; environmental testing; failure modes; fine pitch interconnects; high density interconnections packaging; micro interconnects; micro joints inspection; particle deformation; polymer arrayed particles; precondition test; reliability test; scanning acoustic tomography; scanning electron microscopy; size 30 mum; solder micro bumps; thermal damage; thermal stress; three-dimensional chip stacking; Bonding; Joints; Reliability; Resistance; Silicon; Stacking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575552
Filename :
6575552
Link To Document :
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