Title :
Process integration of 3D Si interposer with double-sided active chip attachments
Author :
Pei-Jer Tzeng ; Lau, John H. ; Chau-Jie Zhan ; Yu-Chen Hsin ; Po-Chih Chang ; Yiu-Hsiang Chang ; Jui-Chin Chen ; Shang-Chun Chen ; Chien-Ying Wu ; Ching-Kuan Lee ; Hsiang-Hung Chang ; Chun-Hsien Chien ; Cha-Hsin Lin ; Tzu-Kun Ku ; Ming-Jer Kao ; Ming Li ;
Author_Institution :
Electron. & Optoelectron. Res. Labs. (EOL), Ind. Technol. Res. Inst. (ITRI), Hsinchu, Taiwan
Abstract :
A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.
Keywords :
elemental semiconductors; integrated circuit interconnections; silicon; three-dimensional integrated circuits; 3D integrated circuits; 3D interposer; RDL; Si; TSV; active die; double sided active chip attachments; double sided chip assembly process; double sided passive interposer; passive electrical characterization; process integration; redistribution layer; size 10 mum; size 100 mum; through silicon vias; Joining processes; Random access memory; Silicon; Stacking; Substrates; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4799-0233-0
DOI :
10.1109/ECTC.2013.6575555
