DocumentCode :
628366
Title :
Low cost, room temperature debondable spin-on temporary bonding solution: A key enabler for 2.5D/3D IC packaging
Author :
John, Ranjith S. E. ; Meynen, Herman ; Sheng Wang ; Peng-Fei Fu ; Yeakle, Craig ; Kim, Sang Wook W. ; Larson, Lyndon J. ; Sullivan, Shawn
Author_Institution :
Dow Corning Corp., Midland, MI, USA
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
107
Lastpage :
112
Abstract :
We report the development of a bi-layer spin on temporary bonding solution (TBS) which eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post treatment for debonding. Thus it greatly increases the throughput of the temporary bonding/debonding process. It also provides a total thickness variation (TTV) of less than 1 μm for spin coated films on both 200 mm and 300 mm wafers which enable the TTV of 300 mm bonded pairs to be 2-3 μm for bumped wafers using 70 and 100 μm thick adhesive films after backgrinding for an unoptimized bonding process. Furthermore, we have demonstrated the chemical and thermal stability of both the material and the bonded pair by exposing the bonded wafer pair to common chemicals (phosphoric acid, nitric acid, organic solvents etc.) and temperature conditions (up to 300 C) used in the TSV process. Additionally, the time taken for the entire spin coat-bond-debond process was less than 15 minutes with room for further improvement. Based on the current results, it is expected that the current bi-layer based temporary bonding solution has the potential to play an important role in enabling the high volume manufacturing of 2.5D/3D IC stacking.
Keywords :
integrated circuit bonding; integrated circuit manufacture; integrated circuit packaging; spin coating; thermal stability; three-dimensional integrated circuits; 3D integrated circuit packaging; TBS; TSV process; TTV; backgrinding; debondable spin-on temporary bonding solution; size 100 mum; size 2 mum to 3 mum; size 200 mm; size 300 mm; size 70 mum; spin coat-bond-debond process; temperature 293 K to 298 K; thermal stability; through-silicon-via; total thickness variation; wafer pair; wafer post treatment; wafer pretreatment; Bonding; Chemicals; Coatings; Films; Integrated circuits; Thermal stability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575558
Filename :
6575558
Link To Document :
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