DocumentCode
628408
Title
Fracture mechanics life-time modeling of low temperature Si fusion bonded interfaces used for 3D MEMS device integration
Author
Naumann, Felix ; Bernasch, Michael ; Siegert, Joerg ; Carniello, S. ; Petzold, M.
Author_Institution
Fraunhofer Inst. for Mech. of Mater. IWM, Halle, Germany
fYear
2013
fDate
28-31 May 2013
Firstpage
390
Lastpage
396
Abstract
In addition to through silicon vias (TSV), wafer bonding became one of the key process steps within 3D integration technologies that allows stacking image or MEMS sensor chips on top of ASIC. Depending on the package, the wafer bonded interface can be loaded by built-in residual stresses and the risk of defect generation and propagation - caused by stress corrosion of the highly loaded siloxane - can lead to bond delamination and failure of the TSV interconnects. In this paper, the basic processes affecting the long-term strength properties in Si bonded interfaces are discussed and summarized on a specific demonstrator. Using finite-element simulation, it is shown that if low temperature Si fusion bonded components are mechanically stressed for extended times a subcritical crack growth of pre-existing micro-defects can occur. Fracture mechanics approaches were applied to predict the time-dependent strength reduction of initial defects, analyzed by Scanning-Acoustic-Microscopy. In addition, the paper presents a general framework of how the life-time properties of loaded low temperature fusion bonded interfaces can be simulated and how the needed material parameters can be determined. Using this method it is possible to consider the life-time properties already during the design stage, thus, reducing the risk of reliability issues during field use.
Keywords
application specific integrated circuits; cracks; delamination; elemental semiconductors; finite element analysis; fracture mechanics; integrated circuit interconnections; internal stresses; microsensors; risk analysis; semiconductor device packaging; semiconductor device reliability; silicon; stacking; three-dimensional integrated circuits; 3D MEMS device integration; ASIC; MEMS sensor chips; Si; TSV interconnect failure; bond delamination; built-in residual stresses; defect generation risk; finite-element simulation; fracture mechanics life-time modeling; fusion bonded components; life-time properties; low temperature fusion bonded interfaces; mechanical stress; microdefects; reliability risk; scanning acoustic microscopy; siloxane; stacking image; stress corrosion; subcritical crack growth; temperature fusion bonded interfaces; through silicon vias; time-dependent strength reduction; wafer bonded interface; wafer bonding; Plasma temperature; Silicon; Stress; Surface treatment; Temperature; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location
Las Vegas, NV
ISSN
0569-5503
Print_ISBN
978-1-4799-0233-0
Type
conf
DOI
10.1109/ECTC.2013.6575600
Filename
6575600
Link To Document