DocumentCode :
628422
Title :
Warpage analysis and improvement for a power module
Author :
Yong Liu ; Yumin Liu ; Zhongfa Yuan ; Chen, T. ; Keunhyuk Lee ; Belani, Suresh
Author_Institution :
Fairchild Semicond. Corp., Portland, ME, USA
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
475
Lastpage :
480
Abstract :
Comparing with the single-chip power packages, the power modules usually have a much larger size due to multiple die built inside. This may induce quite a big package warpage in the assembly process, especially after molding, which makes the package warpage big impact on the DBC substrate, as well as on the silicon die when mounting the power module to an external heat sink during application. Therefore, in this paper, the warpage after molding process of a power module is investigated, and an improvement method is introduced. After molding, the DBC side of the power module may have convex warpage. To reduce the convex warpage, the pre-concave warpage of the DBC substrate is generated during molding process, to balance off part of the convex warpage. However, the concave profile at the DBC side may cause some flash issue around the DBC area during transferring molding process. Both FEA modeling and practical measurement of the package warpage of the power module are conducted thoroughly. It is found that the trends of FEA simulation results are consistent with the measurement data for the package warpage. By balancing off the warpage issue and flash issue, a better option of the preconcave warpage of the DBC substrate is presented for mass production.
Keywords :
electronics packaging; elemental semiconductors; finite element analysis; microprocessor chips; moulding; silicon; DBC area; DBC substrate; FEA modeling; FEA simulation; Si; assembly process; convex warpage; flash issue; heat sink; mass production; measurement data; molding process; package warpage; power module; preconcave warpage; single-chip power packages; warpage analysis; Ceramics; Compounds; Heat sinks; Multichip modules; Power measurement; Semiconductor device measurement; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575614
Filename :
6575614
Link To Document :
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