3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

Author

Coudrain, P. ; Henry, David ; Berthelot, Audrey ; Charbonnier, Jean ; Verrun, S. ; Franiatte, R. ; Bouzaida, N. ; Cibrario, G. ; Calmon, Francis ; O´Connor, Ian ; Lacrevaz, Thierry ; Fourneaud, L. ; Flechet, Bernard ; Chevrier, Norbert ; Farcy, A. ; Le-Br

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

28-31 May 2013

Firstpage

674

Lastpage

682

Abstract

This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.

Keywords

CMOS image sensors; coprocessors; microassembling; semiconductor device packaging; three-dimensional displays; wafer level packaging; 3D circuit; 3D integration; CMOS image sensor; TSV last; coprocessor; design flow; face-to-back integration scheme; image signal processor; microbump technology; nomadic imaging systems; size 200 mm; wafer level; Coprocessors; Image sensors; Lithography; Passivation; Prototypes; Silicon; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Conference_Location

Las Vegas, NV

ISSN

0569-5503

Print_ISBN

978-1-4799-0233-0

Type

conf

DOI

10.1109/ECTC.2013.6575646

Filename

6575646