Large silicon, glass and low CTE organic interposers to printed wiring board SMT interconnections using copper microwire arrays

This paper reports SMT-compatible stress-relief microwire arrays in thin polymer carriers, as a unique, novel and low-cost solution for reliable board-level interconnections between large silicon, glass and low coefficient of thermal expansion (CTE) organic interposers and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled onto the back of the interposer as a stress-relief interlayer. Such a structure is assembled onto the board using standard SMT processes. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (300-400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. The first part of the paper describes the design of microwire array to meet the thermo-mechanical reliability requirements. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. Strip models were built to study the reliability of 400 μm-pitch interconnections with a 100 μm thick, 20 mm × 20 mm silicon interposer that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared with that of ball grid array (BGA) interconnection, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of the microwire array. Flexible thermoplastic polyimide films were used as the polymer film carriers for the microwire interconnection structure. In the in- tial feasibility demonstration, 100 μm thick films with laminated copper foil on both sides of the dielectric were used. A 308 nm excimer laser source was used to ablate the via arrays in the polymer. The microwires were batch fabricated by bottom-up electrolytic plating through the polymer template. A low-cost approach to the microwire fabrication is thus demonstrated by partially releasing the wires with controlled etching of the polymer carrier.