Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network

The equivalent circuit of an on-chip power distribution network (PDN) has a fine 3-D grid structure due to microvias between equipotential conductors and vertical couplings between power and ground lines. Therefore, the 3-D stacked IC tends to be a tightly coupled large network. For the simulation of this type of network, an explicit time marching scheme has an advantage over conventional general-purpose circuit simulators such as SPICE in the computational cost. However, the explicit method has a strict numerical stability condition, which limits the time step size and increases the total amount of the cost. In this work, we propose the method which is explicit, but stable with no stability condition. Additionally, the proposed unconditionally-stable explicit method is accelerated by combining with an order reduction technique.