Harmonic Rejection Mixing Techniques Using Clock-Gating

In this paper, harmonic rejection (HR) mixing techniques to obtain a high level of HR are described. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. A design fabricated in a 110-nm CMOS process rejects up to the first 14 local oscillator (LO) harmonics and achieves third, fifth, and seventh HR ratios in excess of 52, 54, and 55 dB, respectively, without any calibration or trimming. This mixer also rejects flicker noise and has improved quadrature matching and IIP2 performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in a 55-nm standard CMOS process has a programmable number of 8, 10, 12, or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the third harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm.