Fast voltage drop modeling of power grid with application to silicon interposer analysis

Fast and accurate voltage (IR) drop analysis is essential for integrated circuit (IC) and system design. On-chip power grids are usually made of dense rails. Their electrical model consists of a huge number of lumped circuit elements, and its solution consumes much CPU time. Several numerical methods have been proposed in the open literature to address the above issue. Besides numerical methods, effective resistance approach has also been explored for fast IR drop analysis. However, the effective resistance formula used in the previous works is only applicable to an infinite uniform resistor mesh. Recently we have extended the effective resistance approach by using a new closed-form effective resistance formula. Such an extension warrants that the effective resistance approach for fast IR drop analysis is applicable to finite power grid modeling and the accuracy of the simulation results is improved without sacrificing much of the simulation speed. However, we found through further numerical experiments that the accuracy of the results drops when the effective resistance approach is applied to simulate power grids with multiple voltages sources. The relative error of the simulation results compared to the SPICE simulation can reach as large as 5%. We thus propose to use those results as initial guessing values for the iterative method, so as to reduce the number of iterations and further speeds up the simulation by the iterative method. Several numerical experiments including a power grid designed on through-silicon interposers (TSI) are used to demonstrate the proposed approach.