• DocumentCode
    628537
  • Title

    Optimization of solder height and shape to improve the thermo-mechanical reliability of wafer-level chip scale packages

  • Author

    Su-Chun Yang ; Chung-Jung Wu ; Da-Yuan Shih ; Chih-Hang Tung ; Cheng-Chang Wei ; Yi-Li Hsiao ; Ying-Jui Huang ; Yu, Douglas Chen-Hua

  • Author_Institution
    TSMC R & D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
  • fYear
    2013
  • fDate
    28-31 May 2013
  • Firstpage
    1210
  • Lastpage
    1218
  • Abstract
    This study focuses on the development of a highly reliable solder bumping solution by the optimization of bump height and shape for flip-chip mounting of large die directly on PCB without the use of underfill. To achieve the goal, an elongated solder joint with an optimized shape has been developed that demonstrated far superior board-level thermo-mechanical reliability to that of the conventional BGA bumps. When tested at the 7.2×7.2 mm2 die size, the first thermal cycling failure of the improved joint exceeded 800 cycles with the characteristic lifetime reaching 989 cycles without the use of underfill. Experimental result was correlated with FEM analyses to optimize the bump height and shape in order to identify the lowest maximum strain along with improved strain distribution that could lead to the longest lifetime. Moreover, unlike the standard BGA joint where a single crack propagated near UBM is the norm, the fatigue behavior of the optimized joint clearly demonstrated a superior ability to deform along the whole length of the joint. Multiple cracks were constantly observed in the elongated joint indicating the newly designed joint has better capability to absorb stresses and, as a consequence, deforming instead of cracking, that ultimately lead to significantly improved fatigue lifetime.
  • Keywords
    ball grid arrays; chip scale packaging; cracks; fatigue; finite element analysis; flip-chip devices; optimisation; printed circuits; reliability; solders; BGA bumps; FEM analysis; PCB; UBM; cracking; fatigue behavior; fatigue lifetime; flip-chip mounting; optimization; single crack; solder bumping solution; solder height; solder joint; solder shape; thermal cycling failure; thermomechanical reliability; wafer-level chip scale packages; Fatigue; Joints; Reliability; Shape; Soldering; Strain; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
  • Conference_Location
    Las Vegas, NV
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4799-0233-0
  • Type

    conf

  • DOI
    10.1109/ECTC.2013.6575729
  • Filename
    6575729